Low power FPGA solution for GPON burst mode receiver

Broadband services can support triple applications (ie, support for voice, video, and data) up to the first mile of customers, such as small businesses and residences that continue to grow. The protagonist in FTTx is GPON (Gigabit Passive OpTIcal Network), which provides a higher bandwidth alternative to DSL and cable-based fiber-based networks. Due to the effective increase in bandwidth, it is expected that GPON will exceed EPON (Ethernet Passive OpTIcal Network), so GPON will be selected as the technology for the first mile network in the future.

GPON function list

GPON is a time division multiplexing (TDM) system. Based on the reuse of existing facilities, when data is transmitted from the far end, time slots are allocated to end users. As shown in Figure 1, there are two main data streams in GPON. The downstream direction is from OLT (Optic Line Terminal, OpTIcal Line Terminal) to optical splitter, and propagates data to multiple ONUs (Optical Network Units). in

In the upstream direction, the process is reversed. Each user (ONU) is assigned a time slot to transmit data, which is then combined with other data on a single fiber and sent to the central office equipment (OLT). The ONUs are separated from each other. The ONU source data is composed of burst data. Due to the different optical lengths of multiple ONUs, the internal phase in the upstream data changes and conflicts will occur. The challenge of the OLT is to revise the arrangement of each ONU and ensure that each burst of data is synchronized in the upstream optical link.

In the OLT, the lock time requirement of the upstream channel to process these high-speed burst data is very challenging (the typical value for GPON is 50 bits), but the lock time of traditional XAUI or SERDES-based SONET / SDH is very long Thousands of bits). As a result, customers have to use special, discrete burst mode receivers (BMR). However, traditional BMR consumes a lot of power and is difficult to upgrade, resulting in the inability to optimize the volume, which ultimately increases the cost of the system.

Figure 1 GPON optical network

So far, there is no special solution to these special BMRs. However, with the advent of FPGAs, they support fast locking, short execution time, and integrated BMR functions supporting speeds up to 2Gbps.

Ideal BMR

As mentioned earlier, in order to deal with the dynamic nature of the upstream path, BMR must meet a specific set of requirements. The ideal BMR should have a very fast lock time, support high-speed serial data rates, while maintaining a minimum size and minimum power consumption. Traditional BMR has provided data rates for GPON, but has made some tradeoffs in terms of cost, power consumption, and board area. On the other hand, FPGAs provided flexibility and high integration in the past, but the SERDES of these FPGAs could not meet the lock time and data rate requirements of GPON. The ideal solution depends on BMR and FPGA. The current solution is the current FPGA I / O capability. The unique function of these programming platforms is to terminate the upstream PON channel on each pin. Compared with traditional BMR devices, they provide cost-saving and scalable solutions. The most common method currently used is to sample input data with an FPGA.

Figure 2 Embedded high-speed I / O system

This method focuses on performance and power consumption. FPGA provides another method for PON terminal, this FPGA is LatticeSC series. These devices meet the challenges of BMR by incorporating special logic within each I / O, and can dynamically adapt to different lines without using FPGA logic.

As shown in Figure 2, what is embedded in each I / O is the input delay block (INDEL) and adaptive input logic (AIL), which dynamically compensates for changes in the timing phase to achieve a speed of 2Gbps per pin. The result of the terminal is a complete I / O system that supports fast lock time and the performance of traditional BMR, but has a high degree of integration and is a low-power programming platform.

Figure 3 AIL data delay waveform delay line and capture window

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