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Implementation of Rate Matching Algorithm Based on FPGA
LTE (Long Term Evolution) is a global standard for 3.9G wireless communication systems. It utilizes OFDM (Orthogonal Frequency Division Multiplexing) and MIMO (Multiple-Input Multiple-Output) technologies as the core for its wireless network evolution, significantly enhancing system bandwidth [1]. One of the key components in the LTE system is rate matching, which plays a critical role in ensuring efficient data transmission. The quality of the rate matching design directly impacts the overall performance of the system [2]. In LTE, rate matching refers to the process of puncturing or repeating bits on the transport channel to align with the capacity of the physical channel. When the number of input bits exceeds the physical channel's capacity, some bits are removed (punctured). Conversely, if the number of input bits is less than the required capacity, the sequence is repeated to fill the gap. Depending on the coding method used, rate matching can be categorized into convolutional coding-based and Turbo coding-based approaches. Field Programmable Gate Arrays (FPGAs) offer high performance in digital signal processing tasks. Implementing ping-pong operations on an FPGA can greatly enhance the speed and efficiency of data processing [3].
**1 Rate Matching Algorithm**
**1.1 Overall Process of Rate Matching**
In the LTE system, the rate matching process based on Turbo coding is illustrated in Figure 1. This process involves several key steps: sub-block interleaving, bit collection, bit selection, and pruning [4].
**2.2 FPGA Implementation of Ping-Pong Front Control Module**
After passing through the Turbo encoder, the data is temporarily stored in three RAMs. When the enable signal Rate_Match_En in the rate matching module is activated, all modules begin their operation. If the start signal Control_Start of the ping-pong front control module is high and the number of received code blocks is even, the start signal InterleaverA_Start of the sub-block interleaver A module is triggered, allowing it to read data from the external RAM and perform sub-block interleaving. Otherwise, the start signal InterleaverB_Start of the sub-block interleaver B module is activated, and it reads data from the external RAM to carry out the same interleaving process. This mechanism enables a ping-pong operation, effectively managing data flow between different memory blocks and improving the overall throughput of the system.