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The basic principle and debugging principle of jtag
JTAG, originally designed for chip testing, operates by embedding a Test Access Port (TAP) within the device. This TAP allows engineers to access and test internal nodes using a dedicated JTAG tool. One of the key advantages of JTAG is its ability to connect multiple devices in a chain, forming a JTAG chain that enables individual testing of each component. Over time, the JTAG interface has also become widely used for In-System Programming (ISP), particularly for devices like Flash memory.
The JTAG programming method supports online programming, which streamlines the production process. Traditionally, chips were pre-programmed before being mounted on a board. With JTAG, however, the device can be fixed to the circuit board first, and then programmed through the JTAG interface, significantly accelerating project development. This technique is especially useful for programming all components inside a PSD chip.
In simple terms, JTAG works by defining a TAP inside the device, allowing engineers to test and debug internal signals using a specialized JTAG tool. This capability makes JTAG an essential tool for both testing and debugging.
**Boundary Scan**
Boundary scan technology enhances the JTAG system by adding shift register cells at each input and output pin of the chip. These registers, known as boundary scan registers, are positioned along the edge of the chip, hence the name. They play a critical role in JTAG debugging by isolating the chip from its surrounding circuitry, enabling observation and control of input and output signals.
For input pins, boundary scan registers can load data into the pin, while for output pins, they can capture the signal being sent out. These operations occur transparently during normal operation, ensuring that the chip's functionality remains unaffected. Moreover, the boundary scan registers on different pins can be connected to form a boundary scan chain around the chip. This chain allows serial input and output of data via clock and control signals, enabling detailed observation and control of the chip’s I/O states during debugging.
Around the CPU, the JTAG interface is implemented through hardware, with four main pins: TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data In), and TDO (Test Data Out). These pins provide the external connection to the JTAG system.
It's important to note that the term "CPU" here refers to the core arithmetic processing unit, consisting of basic components like internal registers and arithmetic logic units. However, when referring to the processor, it usually means an expanded CPU chip rather than a System-on-Chip (SoC).
JTAG is primarily used for chip testing, with the boundary scan chain being one of its most crucial elements. Located at the edge of the processor, this chain monitors the signals passing through the pins. Since the CPU communicates with peripherals through these pins, JTAG effectively tests the chip by monitoring the signals on them.
As shown in the diagram, the boundary scan chain captures incoming and outgoing signals. When the CPU needs to send a signal, the boundary scan chain can intercept it. Similarly, when a signal is input, the chain can detect it. This allows for precise control and observation of the chip’s behavior.
TDI and TDO serve as the interface for storing these signals. The signal path follows a clear route: TDI → Boundary Scan Chain → TDO. This allows engineers to input custom signals through TDI, shift them through the chain, and read the results through TDO.
The data exchanged between the CPU and external components typically includes command and data signals—such as addresses and data. Together, they form a complete program, and monitoring them provides valuable insight into the chip’s operation. Most chips feature multiple independent boundary scan chains, and their control is managed by the TAP controller.
This is the fundamental principle of JTAG. For more advanced debugging, additional components and complex register configurations are often required to enhance the system’s capabilities.