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The basic principle and debugging principle of jtag
JTAG, originally designed for chip testing, operates by embedding a Test Access Port (TAP) within the device. This TAP allows access to internal nodes through a dedicated JTAG test tool. One of its key features is the ability to connect multiple devices in a chain via the JTAG interface, enabling individual testing of each device. Over time, the JTAG interface has also become widely used for In-System Programming (ISP), particularly for programming devices like FLASH memory.
The JTAG programming method enables online programming, which streamlines the production process. Traditionally, chips were pre-programmed before being mounted on a board. However, with JTAG, the device can be fixed to the circuit board first and then programmed, significantly accelerating project development. This approach supports programming all components within a PSD chip through the JTAG interface.
In simple terms, JTAG works by defining a TAP inside the device, allowing internal nodes to be tested and debugged using a specialized JTAG tool.
**Boundary Scan**
Boundary scan introduces a shift register unit—known as a Boundary-Scan Register Cell—at each input and output pin of the chip. These units, located at the chip's boundary, are referred to as boundary scan registers. Boundary scan plays a crucial role in JTAG debugging. When a chip needs to be debugged, these registers isolate it from the surrounding circuitry, enabling observation and control of its input and output signals.
For input pins, the boundary scan register can load data into the pin. For output pins, the register can capture the signal present on the pin. Under normal operation, these registers remain transparent, ensuring that the chip functions as intended without disruption. Additionally, boundary scan register units on input and output pins can be connected to form a boundary scan chain around the chip. This chain allows serial input and output of data through clock and control signals, enabling observation and control of the chip’s input/output states during debugging.
On the periphery of the CPU, the processor contains hardware that implements JTAG, providing an external interface through four pins: TMS, TCK, TDI, and TDO.
In this context, the CPU refers to the arithmetic processing unit, consisting of basic components such as internal registers and arithmetic logic units. The term "processor" here refers to a CPU expansion chip, not an SoC (System on Chip).
How is JTAG used for chip testing? The most critical component is the boundary scan chain, named for its location at the edge of the processor. We know that the CPU communicates with peripherals through its pins, and all data is transmitted through these pins. JTAG tests the chip by monitoring the signals on these pins. The boundary scan chain is a component located on the pin, as shown below:
Through the boundary scan chain, when a signal is input, the chain can capture it. Similarly, when the CPU wants to output a signal, the boundary scan chain can also capture it or directly send it out. To store these signals, TDI and TDO serve as the interface. As illustrated:
Originally, the boundary scan chain holds the signal on the pin. When we input our own signal through the TDI pin, a shift operation occurs along the red line. The path is: **TDI → Boundary Scan Chain → TDO**. The signal on the boundary scan chain can be retrieved from the TDO, and the signal we input through TDI will also reach the boundary scan chain.
The data on the pin, which the CPU uses to communicate with the outside world, consists of command and data signals, including addresses and data. Together, they form a complete program. By monitoring these signals, we can effectively debug the program. A typical chip may have several independent boundary scan chains. The TAP Controller primarily manages the operation of these chains.
This is the fundamental principle of JTAG. To enhance debugging capabilities, additional control over components and more complex register configurations are often required.