Shaanxi Xinlong Metal Electro-mechanical Co., Ltd. , https://www.cnxlalloys.com
FPGA-based programmable oscillator enhancement
Today's advanced FPGAs are equipped with a variety of functional blocks that enable the implementation of complex circuits and systems, including logic arrays, memory modules, DSP blocks, embedded processors, phase-locked loops (PLLs) for clock generation, delay-locked loops (DLLs), I/O interfaces, high-speed digital transceivers, and parallel interfaces such as PCI and DDR. These components typically operate under multiple clock signals, which are often generated using a combination of external oscillators and internal PLL or DLL circuits. System designers must carefully balance the use of these resources to create an optimal clock distribution network.
A programmable clock oscillator serves as a flexible timing reference for FPGA-based systems, offering significant advantages in both design flexibility and performance. One of its key benefits is the ability to precisely select clock frequencies, allowing for fine-tuning of the clock tree to meet specific application requirements. Additionally, spread spectrum modulation helps reduce electromagnetic interference (EMI), making it ideal for high-performance and noise-sensitive applications.
The inherent programmability of MEMS-based clock oscillators makes them particularly useful for FPGA systems, where they can be integrated with features like spread-spectrum clocks, digitally controlled oscillators for jitter reduction, and fail-safe mechanisms in critical high-speed applications. This level of integration simplifies system design while improving reliability and performance.
In many systems, a range of clock frequencies is required, some of which are standardized due to industry specifications or widespread usage. For example, PCIe requires 100 MHz, SATA uses 75 MHz, and PCITM operates at 33.333 MHz. These standard frequencies ensure compatibility across different interfaces. However, the clock frequency used for processing units like the CPU, DSP, or state machines can be adjusted by the designer to optimize performance, power consumption, or resource utilization.
When optimizing for speed, the processor should run at the highest possible clock frequency to maximize throughput. However, the clock period must have minimal jitter to ensure that the critical timing paths in the design are met. A common approach is to use an internal FPGA PLL to generate a high-frequency clock from a standard external reference. This method works best when the internal PLL has high frequency resolution and low jitter.
Some FPGAs include a low-noise fractional PLL that meets these requirements, allowing the use of a simple external oscillator. However, many FPGAs rely on integer PLLs with ring VCOs and feedback dividers, which are compact, flexible, and power-efficient but may struggle to achieve both high resolution and low jitter simultaneously.
Figure 1 illustrates the general structure of an integer PLL, where the output frequency is determined by the prescaler (P), feedback divider (M), and postscaler (N). The PLL forms a band-limited control system, and the output jitter is influenced by the reference clock phase noise and the internal VCO phase noise. The relationship between these factors is governed by the low-pass and high-pass filter responses within the loop.
Figure 2 shows the transfer functions for input reference phase noise and VCO phase noise in a second-order PLL. The maximum achievable bandwidth depends on the phase detector’s update rate, typically limited to around 100kHz for a 40MHz input frequency with a prescaler of 40.
Jitter is closely related to phase noise, especially at frequencies near half the output frequency. As shown in Figure 4, the impact of VCO phase noise becomes more pronounced at these frequencies, since the PLL bandwidth is much smaller than the output frequency. Increasing the PLL bandwidth can reduce the effect of VCO noise, but this often comes at the cost of reduced frequency resolution.
To address this trade-off, using an external high-resolution oscillator can help maintain both precision and low jitter, providing a more balanced solution for complex FPGA designs.