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Gaoyun Semiconductor Introduces Universal LVDS Transmission Interface Solution
On August 22, 2017, in Foshan, Guangdong, Guangdong Gaoyun Semiconductor Technology Co., Ltd. (referred to as "Gaoyun Semiconductor") announced its latest developments. Gaoyun Semiconductor supports the non-volatile bee® family GW1N series and the medium-density Chenxi® family GW2A. These products include a comprehensive range of solutions such as soft cores, reference designs, and development boards, all centered around the Gowin Generic LVDS Gearbox IP cores.
Gaoyun’s GMDS gearbox interface IP facilitates the conversion between internal logic clock frequencies and data bit widths and ensures data throughput remains consistent. It supports both transmission and reception functions across all FPGA chip transceivers, with transmission ratios of 1:1, 1:2, 1:4, 1:7, 1:8, and 1:10. Additionally, the GW1N-6/9 devices support a 1:16 switching ratio. For channels with different clock and data phase relationships, the high-cloud universal LVDS gearbox interface supports both edge alignment and mid-alignment.
The high-cloud FPGA chip provides a dedicated unit module for constructing a high-speed LVDS interface. This includes integrated unit modules that work together to meet customer-specific bandwidth, alignment, transceiver functions, and switching ratio requirements. Features include:
- High-speed, low-skew clock HCLK for high-performance data transmission;
- Internal system clock GCLK, which must use the global clock network;
- A high-speed clock divider module generating a GCLK synchronized with the input clock HCLK;
- A phase-locked loop module for clock multiplication, division, and phase shifting;
- A serial-to-parallel receiving-side module for gearbox functionality;
- A parallel-to-serial transmitting-side module for gearbox functionality;
- Each I/O includes a delay module providing a total delay of approximately 128 steps x 25ps = 3200ps.
"Gaoyun's Universal LVDS gearbox interface IP fully utilizes the various dedicated unit modules embedded within the high-cloud FPGA chip," explained Gao Yun Product Application Manager Mr. Xu Cai. "This allows the high-speed FPGA device LVDS I/O interface to reach performance requirements of 800Mbps to 1.2Gbps. In the TCON market application, the FPGA controls the timing actions of the LCD screen, converting input video signals like LVDS into formats suitable for data driving circuits like Mini-LVDS or RSDS, ensuring the data driver circuit turns on at the right time. The high-cloud FPGA chip aligns with TCON market demands regarding LVDS differential pin counts and LVDS interface performance."
"Video acquisition and display technologies are advancing rapidly. High-speed LVDS-based interfaces like Mini-LVDS, MIPI CSI-2/DSI are now widely used in mobile phones, tablets, VR, and unmanned applications," said Gao Yun Semiconductor Market Vice President and China Sales Director Huang Jun. "There is an increasing demand for bridging and image processing of video interfaces in consumer electronics, automotive electronics, and industrial displays. Gaoyun Semiconductor has introduced a universal LVDS gearbox interface solution combining the advantages of high-power semiconductor FPGA chips, including non-volatility, small-thin packaging, embedded high-capacity SDRAM, and others, offering users in these markets solutions for video interface bridging and image processing to accelerate time to market."
**Key Features of the IP**
- Current LVDS I/O data rate: 1.2Gbps;
- Internal fabric clock rate: 120MHz for the GW1N series and 200MHz for the GW2A series.
**TCON System Architecture and IP Calls**
Video image data is converted into a parallel video signal by the LVDS 7:1 receiving module and then processed into the required image format by the image processing module. Finally, it is transmitted to the LCD screen via the mini-LVDS 4:1 transmitting module.
GW1N/1NR and GW2A/2AR series FPGA chips support various differential level standards such as LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVCECLE, and RSDSE. They integrate multiple gear ratios for the switching ratio.
**Development Board and Reference Design**
Gaoyun GMDS gearbox interface IP, reference designs, and development boards support the GW1N-4K FQPF144 package FPGA chip for LVDS receive signals and mini-LVDS transmit signals. Future upgrades will support the GW2A series FPGA chip, enhancing LVDS I/O interface performance further.
**About Gaoyun Semiconductor**
Established in January 2014, Guangdong Gaoyun Semiconductor Technology Co., Ltd. is committed to developing domestic FPGA solutions and promoting their industrialization. The company aims to launch a national brand FPGA chip with core independent intellectual property rights. Gaoyun Semiconductor offers users the highest quality service, providing one-stop services including chips, design software, soft cores, reference designs, and demonstration boards.
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